Display devices have become thinner and larger as industrial utilization has increased. Among the various types of flat panel display (FPD) devices, liquid crystal display (LCD) devices and plasma display panel (PDP) devices are widely used. LCD devices are widely used as monitors for notebook computers and desktop computers because of characteristics such as light weight, portability and low power consumption. Specifically, active matrix type LCD devices having thin film transistors (TFTs) as switching elements have been researched and developed due to the quality of the display of moving images.
The LCD device uses optical anisotropy and polarization properties of liquid crystal molecules to display images. The liquid crystal molecules have orientation characteristics of arrangement resulting from their thin and long shape. Thus, an arrangement direction of the liquid crystal molecules can be controlled by applying an electrical field to them. Particularly, the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images. Since the LCD device includes the TFT as the switching element, it may be referred to a TFT-LCD device.
FIG. 1 is a schematic block diagram of a liquid crystal display device according to the related art. In FIG. 1, the liquid crystal display device includes a liquid crystal panel 2 and a liquid crystal module (LCM) driving circuit unit 26. The LCM driving circuit unit 26 includes an interface 10, a timing controller 12, a source voltage generator 14, a reference voltage generator 16, a data driver 18 and a gate driver 20. The data driver 18 may also be referred to as a source driver, which may be distinguished from the source voltage generator 14. The gate driver 20 may be referred to as a gate driving unit. The interface 10 as a driving system, for example, a personal computer, receives data, for example (R), red (G), green (B) and blue data, and control signals, for example, input clocks, a horizontal sync signals, vertical sync signals and data enable signals, inputted into the LCD driving circuit unit 26 from a driving system, for example, a personal computer. Then, the interface 10 outputs the RGB data and control signals to the timing controller 12. For example, a low voltage differential signal (LVDS) interface and transistor-transistor logic (TTL) interface may be used for transmission of the RGB data and the control signals. In addition, the interface 10 may be integrated on a single chip together with the timing controller 12.
Referring to FIG. 2 showing a liquid crystal panel of the liquid crystal display device according to the related art, a plurality of gate lines “GL1” to “GLn” and a plurality of data lines “DL1” to “DLm” are formed on a glass substrate to define a plurality of pixel regions. Each of a thin film transistor (TFT) and a liquid crystal (CLC) is formed in each pixel region such that the liquid crystal display device can display an image.
Referring back to FIG. 1, the timing controller 12 generates data control signals for the source driver 18 including a plurality of data integrated circuits (ICs), and gate control signals for the gate driving unit 20 including a plurality of gate ICs. In addition, the timing controller 12 outputs data signals from the interface 10 to the source driver 18.
The reference voltage generator 16 generates reference voltages of a digital-to-analog converter (DAC) used in the source driver 18. The reference voltages are set up according to transmittance-voltage characteristics of the liquid crystal panel 2.
The source driver 18 determines the reference voltages for the data signals according to the control signals from the timing controller 12 and outputs the determined reference voltages to the liquid crystal panel 2 to adjust a rotation angle of liquid crystal molecules.
The gate driving unit 20 controls ON/OFF operation of the thin film transistors (TFTs) in the liquid crystal panel 2 according to the control signals from the timing controller 12. The gate driving unit 20 enable supplies scanning signals to the gate lines GL1 to GLn of the liquid crystal panel 2. Accordingly, the data signals from the source driver 18 are supplied to pixels in the pixel regions of the liquid crystal panel 2 through the TFTs. The source voltage generator 14 supplies source voltages to elements of the LCD device and a common voltage to the liquid crystal panel 2.
Although not shown in FIGS. 1 and 2, a backlight unit including at least one lamp is disposed under the liquid crystal panel 2 to supply a light to the liquid crystal panel 2.
FIG. 3 shows a gate driving unit accordingly to the related art. In FIG. 3, each of first to nth shift registers SR1 to SRn supplies an output, for example, first to nth gate voltages Vg1 to Vgn, according to one of the clock signals CLK1 and CLK2. The clock signals CLK1 and CLK2 are input into a clock signal terminal CLK. For example, an output of the nth shift register SRn is input into a start signal terminal STR for being used for a start signal Vst of previous shift register. The output of the nth shift register SRn is input into a reset signal terminal RST for being used for a reset signal of next shift register. As a result, the gate driving unit 20 outputs sequential timing scanning signals Vg1 to Vgn, as shown in FIG. 4 showing a signal timing chart of a scanning signal from a gate driving unit according to the related art.
Although not shown, each of the shift registers SR1 to SRn receives a high level driving voltage VDD and a low level driving voltage VSS for driving thereof. In addition, the last nth shift register SRn receives a reset signal Vrst through a separating way. The gate driving unit 20 includes a redundant repair shift register SR(r) and a plurality of repair lines RL for repairing disordered shift registers of the first to nth shift registers SR1 to SRn. With the redundant repair shift register SR(r) and the plurality of repair lines RL, when at least one shift registers of the first to nth shift registers SR1 to SRn is broken down, the redundant repair shift register SR(r) functions as the disordered shift register, as shown in FIG. 5 showing a repairing method of the gate driving unit according to the related art.
In FIG. 5, when the second shift register SR2 is broken down, input and output lines of the second shift register SR2 is disconnected by a laser. Then, a line of the redundant repair shift register SR(r) is connected to the repair line RL by a laser welding such that the redundant repair shift register SR(r) is used for outputting the second scanning signal V2 instead of the second shift register SR2.
Unfortunately, the above-mentioned repairing method using the redundant repair shift register has some problems. Referring to FIG. 6, the fairer a distance between the repair shift register and the disordered shift register is, the greater load there is on the input and output lines. Accordingly, there is a signal distorting in the output signal. This problem is outstanding in case that the shift registers SR1 to SRn and the TFTs are formed at edges of the substrate at the same time. This is referred to as a gate in panel (GIP) type.